The present invention relates generally to processing within a computing environment, and more specifically, to a computing system with a multilevel cache hierarchy.
A cache is generally a memory that store copies of data from the most frequently used system memory locations such that future request for data may be served faster. A multiprocessor computing system includes multiple processing units that are coupled to one another, and share a system memory. In order to reduce access latency to data and instructions residing in the system memory, each processing unit may be supplied with a multi-level cache hierarchy. For example, a level one (L1) cache may have a lower access latency than a level two (L2) cache, the L2 cache may have a lower access latency than a level three (L3) cache, and the L3 cache may have a lower access latency than a level four (L4) cache. Cache operations in a multilevel cache hierarchy are controlled by a cache controller. Within a cache, data are organized and tracked on a cache line basis, where a typical cache line contains a fixed number of bytes, for example, 256 bytes. Each level of cache has an associated directory to keep track of which lines of cache are stored in the specific cache.
Embodiments include a system and computer program product for accessing a cache line on a multi-level cache system having a system memory. Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests are concurrently sent to the system memory and remote nodes of the plurality of nodes for the specific cache line by the local node. The specific cache line is found in a specific remote node. The specific remote node is one of the remote nodes. The specific cache line is removed from the specific remote node for exclusive ownership by another node. Based on the specified node having the specified cache line in ghost state, any subsequent fetch request initiated for the specific cache line from the specific node encounters the ghost state. When the ghost state is encountered, the subsequent fetch request is directed only to nodes of the plurality of nodes. The subsequent fetch is absent of a concurrent fetch request to system memory.
In another approach to obtain the requested cache line, the cache controller may initiate a fetch request to only the other caches first, which reduces unnecessary usage of associated buffers and control logic needed for system memory fetches. However, the cache controller is unable to determine ahead of time if a fetch to the caches or nodes will be successful. Thus, the cache controller has to wait to determine if the fetch is successful before initiating a fetch operation to the system memory, which increases latency.